This invention relates to analog to digital converters and more particularly to analog to digital converters having means for compensating for offset errors so as to provide for an accurate conversion. The invention is particularly adaptable to analog to digital conversion in those applications where a microcomputer is used since the conversion incorporates the microcomputer to select the voltages applied to the integrating circuitry and to provide the counting or timekeeping function of the converter.
Analog to digital converters of various types have been in use for many years. Among the converters most frequently used is the dual slope analog to digital converter such as described, for example, in U.S. Pat. No. 3,051,939. Improvements have been made in the dual slope analog to digital converter to incorporate provisions for compensating for the offset error and to provide for bipolar operation without zero discontinuity as shown, for example, in U.S. Pat. No. 3,872,466 as well as the Continuation-in-Part of that patent, namely U.S. Pat. No. 3,942,173. In these patents, a linear integrator is operated through two successive cycles to effect the analog to digital conversion. In the first of these two cycles, an error signal is derived representing the total error producing offset voltage present in the system. In the second cycle, the unknown analog signal is converted to a corresponding digital output signal by an arrangement which corrects the digital output for the error component previously determined in the first cycle. The correction is accomplished by determining the integrating period during which the unknown voltage is integrated so that the time period for that integration is modified in accordance with the magnitude of the error signal detected during the first cycle.
Another approach to correction for the offset error is disclosed in U.S. Pat. No. 4,023,160 which also includes two cycles but which does not utilize the determination during the error signal measuring cycle to determine the duration of the integration of the unknown during the second cycle. Instead, this reference utilizes a counter which counts in one direction during the discharge portion of the first cycle and that counter is then utilized to count in the opposite direction during the discharge portion of the second cycle so that the net count resulting is intended to provide a digital signal corresponding to the analog signal with compensation for offset error. This latter method of error compensation will not, however, compensate for the effect of the error signal on both the charging and discharging of the integrator as is the case with the previous references mentioned. Likewise, the arrangement shown in U.S. Pat. No. 4,023,160 does not carry out the integration only on one side of the predetermined datum voltage level. Therefore, the arrangement of U.S. Pat. No. 4,023,160 is subject to errors resulting from variations in the response of the converter component such as the comparator used as a zero crossing detector, whereas in the arrangement of U.S. Pat. Nos. 3,872,466 and 3,942,173, as in the present invention, the integrator is operated so as to carry out the integration only on one side of a predetermined datum voltage level with the functioning of the converter to be the same for input analog signals of either polarity and with no special means needed to provide for sensing the input polarity and for switching the converter circuitry accordingly as in conventional bipolar converters of the dual slope type. Thus, the single sided integration operation of those two references is carried out in such a way that the ramp approach to and the intersection with the datum level always is from the same direction, and always is at the same slope. The conversion operation is started in response to the detection of the integrator output crossing the datum level, such as ground level, from that same direction and slope so that errors due to varying response time in the comparator for determining when that level is arrived at will not be variable.
It will be evident that none of the prior art references correct for long term changes in offset currents and voltages which result in span shifts.
It is an object of the present invention to avoid the complexities of the prior art analog to digital converters described above, by providing a converter which will correct for offset errors which vary during long term operation as, for example, due to temperature and time thus correcting for the resulting span shift. The invention also provides a means whereby analog to digital conversion can be carried out with a minimum of components and with the least expensive components. The present invention is particularly applicable in those applications where a microcomputer is to be used for computational purposes other than those required as part of the analog to digital converter. Other objects and advantages of the invention will become evident from the following description considered together with the accompanying drawings.